Field of the Invention
The present invention relates to a video data processing apparatus, and in particular relates to encoding of video by such a video data processing apparatus.
Description of the Prior Art
Contemporary encoding standards, such as H.264, incorporate many advanced techniques to achieve a high degree of coding efficiency, for example multi-picture inter-picture prediction, intra-coding and various entropy encoding techniques. Nevertheless, despite the great advances in encoding efficiency that have been achieved, video system designers naturally continually strive to design video systems which operate at (or close to) the achievable limits of video quality and frame transmission rates.
Although dramatic compression ratios may be achieved by contemporary video encoding standards, video systems for performing encoding must be able to handle the high bandwidths of video data that result from the output of the high resolution and frame rate video cameras that are currently available. Indeed, in such systems the volume of video data traffic is typically the dominant bandwidth on the system bus. A further critical constraint on the system bandwidth is the random access memory bandwidth. The DRAM (Dynamic Random Access Memory) storage units employed by contemporary video systems have a limited bandwidth for accessing their stored data. If the system design requires a higher bandwidth, then this may necessitate the inclusion of an additional DRAM device, which in certain space-limited systems (such as embedded video encoders) may not be viable. Hence it will be recognised that bandwidth at the system level is a critical parameter in such systems.
Nevertheless, it is well known that consumers are hard taskmasters, continually demanding higher specifications and new features from contemporary video systems. For example, a slow motion capability on video cameras is a popular feature, yet the increased frame rate that this requires can be become a serious demand on the system bandwidth. A typical encoding pattern for video data comprises an initial intra-coded frame (“I-frame”) followed by a series of predicted pictures (“P-frames”) which are each predicted with reference to the previous frame. Since video data bandwidth increases approximately linearly with frame rate, there may be little capacity for an increase in frame rate in a video system which is already operating close to its full bandwidth capacity.
Some papers which discuss implementations of H.264 encoding and decoding are: “Implementation of H.264 Encoder and Decoder on Personal Computers”, Y.-K. Chen, E. Q. Li, X. Zhou, and S. L. Ge, in Journal of Visual Communications and Image Representations, vol. 17, no. 2, pp. 509-532, April 2006; and “Parallel H.264 Decoding on an Embedded Multicore Processor”, Azevedo, A., Meenderinck, C., Juurlink, B., Terechko, A., Hoogerbrugge, J., Alvarez, M., and Ramirez, A., 2009, In Proceedings of the 4th international Conference on High Performance Embedded Architectures and Compilers. 
It would be desirable to provide an improved technique for performing video encoding which enables an increase in frame rate, without a proportional increase in the bandwidth required to handle the consequent video data.